The present invention relates to a double-gate field effect transistor (DGFET) device, and more particularly to a method of forming a planar double-gate field effect transistor having self-aligned front and back gates.
In order to fabricate integrated circuits (ICs), such as memory, logic, and other devices, of higher integration density than currently feasible, one has to find a way to further downscale the dimensions of devices such as field effect transistors (FETs), which are present in an IC.
As FET dimensions are scaled down, FETs suffer from several problems. In particular, interactions between the source and drain of the FET degrade the ability of the gate to control whether the device is on or off. As the device size is reduced, the distance between source and drain regions of the FET is decreased leading to increasing interaction with the channel, thus reducing gate control. This phenomenon is called the xe2x80x9cshort-channel effectxe2x80x9d. Short-channel effects are well known to those skilled in the art as the decrease in threshold voltage, Vt, in short-channel devices, i.e., sub-0.1 micron, due to two dimensional electrostatic charge sharing between the gate and the source/drain regions.
An evolution beyond current CMOS devices is achieved through the application of a double-gate structure, wherein a channel is positioned between a front and a back gate. Positioning a channel between two gate structures allows for control of the gate from either side of the channel, hence reducing short-channel effects. In addition to improved short-channel effects, further advantages of the double-gate structure include, but are not limited to: higher transconductance and lower parasitic capacitance. With the use of a double-gate structure previous CMOS (complementary metal oxide semiconductor) devices can be scaled to half the channel length of conventional single gate structures. Double-gate structures are excellent candidates for future generation of high-performance CMOS devices.
Currently, both vertical and horizontal double-gate structures are being actively developed. The horizontal, i.e., planar, gate structure has several advantages over the vertical gate structures due to the similarity of the current state of the art CMOS devices. One major and formidable challenge of fabricating a planar double-gate device is aligning the back gate to the front gate.
In one prior art method, planar double-gate structures are formed by regrowing the channel after front to back alignment and definition. Another prior art method presently utilized to produce an aligned double-gate structure is to etch the back gate by using the front gate as an etch mask. Following the etching step, source/drain regions are regrown via selective epitaxial Si growth.
These prior methods for producing double-gate devices have numerous drawbacks due to severe difficulty with parameter control of the complex fabrication technology currently utilized in the production of double-gate FET devices. In view of the drawbacks mentioned with prior art methods of fabricating self-aligned planar DGFET devices, there is still a need for providing a new and improved method for fabricating the same. The method developed needs to avoid the fabrication complexity of prior art processes.
The present invention provides a method for fabricating a planar DGFET having a back gate that is aligned to a front gate. The method of the present invention achieves this alignment without experiencing any of the problems associated with prior art front to back gate alignment. The method of the present invention also provides a means for lowering the capacitance between the source/drain regions and the back gate.
In broad terms, the method of the present invention comprises the steps of:
providing a stacked double-gate structure comprising at least a back gate, a back gate dielectric located atop the back gate, a channel layer located atop the back gate dielectric, a front gate dielectric atop the channel layer, and a front gate located atop the front gate dielectric;
patterning the front gate of the stacked double-gate structure;
forming sidewall spacers on exposed sidewalls of the patterned front gate; and
forming a carrier-depleted zone in portions of the back gate, wherein said carrier-depleted zone aligns the back gate to the front gate.
In addition to aligning the back gate to the front gate, the carrier-depleted zone improves device performance by lowering the capacitance between the source/drain regions and the back gate.
In one embodiment of the present invention, the carrier-depleted zone is an amorphous region that is located at the back gate/back gate dielectric interface. In this embodiment, implantation of ions that are capable of forming such an amorphous region is employed. The amorphous region defines the back gate in a self-aligned manner that is easily incorporated into a conventional process flow.
In another embodiment of the present invention, the carrier-depleted zone is a layer of bubbles that is located at the back gate/back gate dielectric interface. The layer of bubbles is created by ion implantation and annealing. The layer of bubbles defines the back gate in a self-aligned manner that is also easily incorporated into a conventional process flow.
Another aspect of the present invention relates to a self-aligned planar DGFET device. Specifically, the inventive DGFET device comprises:
a back gate dielectric located atop a back gate;
a channel layer located atop the back gate dielectric;
a front gate dielectric located atop the channel layer; and
a patterned front gate located atop a portion of the channel region, wherein the back gate contains a carrier-depleted zone which aligns the back gate to the front gate.
The self-aligned planar DGFET of the present invention may also include a back-gate contact which is in contact with a surface portion of the back gate.